module RegBank(clk, srcA, srcB, dstE, valE, dstM, valM, valA, valB, reset);

input clk;
input [3:0] srcA;
input [3:0] srcB;
input [3:0] dstE;
input [31:0] valE;
input [3:0] dstM;
input [31:0] valM;
input reset;

output [31:0] valA;
output [31:0] valB;

reg [31:0] registers [0:8];
//reg [31:0] regEsp;

assign valA = registers[srcA];
assign valB = registers[srcB];

always @(posedge clk or negedge reset) begin

   if(!reset)begin
      registers[0] <= 32'h0;
      registers[1] <= 32'h1;
      registers[2] <= 32'h2;
      registers[3] <= 32'h3;
      registers[4] <= 32'h00000fff;
      registers[5] <= 32'b0;
      registers[6] <= 32'b0;
      registers[7] <= 32'b0;
      registers[8] <= 32'b0;
   
   end
   else begin
      if(dstE != 4'h8)begin
			registers[dstE] <= valE;
      end
      if(dstM != 4'h	8)begin
			registers[dstM] <= valM;
      end
   end
end


endmodule
